1. Field of the Invention
The present invention relates to a semiconductor memory device including a plurality of memories each of which requires refresh in order to maintain the memory contents therein, and a method of refreshing a semiconductor memory device.
2. Description of the Prior Art
Referring now to FIG. 5, there is illustrated a block diagram showing the structure of a prior art semiconductor memory device. In the figure, reference numeral 1 denotes a semiconductor memory circuit including a plurality of memory elements M1 to Mn, such as DRAMs, each for maintaining the memory contents therein within a time period during which refresh is repeated, 2 denotes a refresh request timer circuit for sending out a refresh request at regular intervals, 3 denotes a refreshing circuit for performing a refreshing operation on the plurality of memory elements M1 to Mn included in the semiconductor memory circuit every time it receives a refresh request from the refresh request timer circuit 2.
Thus, the prior art one-chip semiconductor memory device includes the refreshing circuit 3, the refresh request timer circuit 2, and other electronic circuits (not shown), in addition to the semiconductor memory circuit 1. In order for the plurality of memory elements M1 to Mn, of the semiconductor memory circuit 1, to maintain the memory contents over a certain period of time, a process of refreshing the plurality of memory elements, including a process of reading data from each of the plurality of memory elements and a process of rewriting the data into each of the plurality of memory elements in addition to a process of holding the data stored in each of the plurality of memory elements, is needed.
In a conventional manner, every time the refresh request timer circuit 2 makes a refresh request at fixed intervals, the refreshing circuit 3 refreshes the plurality of memory elements Ml to Mn so as to maintain the memory contents in each of them. The refresh request timer circuit 2 makes a refresh request at fixed intervals which have been determined according to the shortest holding time period among the holding time periods for the plurality of memory elements M1 to Mn, during which the memory contents therein can be maintained. The number of memory elements on which the refreshing circuit 3 can perform a refreshing operation at the same time is set to a constant number n. To be more specific, the number of memory elements on which the refreshing circuit 3 can perform a refreshing operation at the same time has to be maintained constant due to the maximum permissible amount of heat generated by the semiconductor memory circuit 1.
Therefore, since, when the number of the plurality of memory elements built in the semiconductor memory circuit is greater than n, the refreshing circuit 3 cannot perform a refreshing operation on all of them at one time, i.e. at the same time, it has to perform a refreshing operation on all of them at several different times.
Japanese Patent Application Laying Open (KOKAI) No. 9-282871 and No. 9-190700 disclose another prior art refresh request timer circuit that can change intervals at which it makes a refresh request.
A problem with such a prior art semiconductor memory device which is so constructed as mentioned above is that while it can perform a refreshing operation on a plurality of memory elements M1 to Mn, the number of memory elements on which the refreshing circuit 3 can perform a refresh operation at the same time is set to a constant number n. Accordingly, the number of memory elements on which the refreshing circuit 3 can perform a refresh operation at the same time cannot be increased even though the semiconductor memory device includes a low-heat-producing semiconductor memory circuit 1 (for example, when a voltage applied to the semiconductor memory circuit 1 is reduced. In this case, the amount of current flowing through the semiconductor memory circuit 1 is reduced and therefore the amount of heat generated by the semiconductor memory circuit 1 is reduced.)